In a digital device, such as a word generator, which generates a data stream at a high speed, the desired data stream is obtained by writing the data stream to be generated in a memory and then reading it out in synchronism with a clock. One example of such a data stream generator known in the prior art, especially its memory and the peripheral portion, is shown in FIG. 3.
In the configuration in FIG. 3, the start address is first set to an address counter 31, and then a clock f.sub.CLK is supplied thereto. Then, the address counter 31 provides the memory 33 with a sequence of the successive addresses starting at the start address in synchronism with the clock f.sub.CLK, and the data read therefrom is temporarily latched in a latch 35 in synchronism with the clock f.sub.CLK. This allows the desired data stream which has been written in advance in the memory 33 between the start and last addresses shown in FIG. 3 to be provided to the latch 35.
The last address is set to an address comparator 37. The addresses generated by the address counter 31 are also provided to the address comparator 37. When the address generated by the address counter 31 coincides with the last address, operation stops. Alternatively, different operations may be taken when the addresses coincide such as resetting the counter to the start address for repeating the same operation, or stopping this repetition when the count of the additional counter which counts the number of the repetition reaches the number of the preset cycle. Though there are a variety of options in the manner as to how the data stream is repeated as explained above, it is in any way difficult to generate the data stream at a high speed with a configuration as shown in FIG. 3 due to the limiting factor of the reading speed of the memory 33.
In order to solve this problem, the prior art employs the configuration shown in FIG. 4, with a memory divided into n banks arranged in parallel, to generate the data stream at a speed higher than that of the memory.
Specifically, in the configuration shown in FIG. 4, the structures of an address comparator 47 and an address counter 41 are essentially the same as their counterparts shown in FIG. 3. In this configuration, a 1/n-frequency divider 401 provides the address counter 41 with the frequency-divided clock signal f.sub.CLK /n. The address output by the address counter 41 is provided to a memory 43 consisting of n banks, bank 1 through bank n, arranged in parallel. Each of banks 1 through n sets the result of reading from the given address into the associated one of latches 1 through n. An n-counter 405 receives the clock f.sub.CLK, and the count output of the counter 405 is provided to the selection signal input of a multiplexer 403. This causes a multiplexer 403 to sequentially select the data stored in the latches 1 through n and output the selected data. With such a structure and control, the data stream can be generated at a speed n times as fast as that of the memory.
However, the conventional configuration shown in FIG. 4 has the serious problem that the length or the period of the data stream that can be generated is limited to a multiple of n. That is, in this configuration, blocks of n pieces of data are simultaneously read from the memory 43, and the multiplexer 403 sequentially selects the latches from the latch group 45 containing the n pieces of data to output. A larger n increases the speed of the data stream generation, but also increases the constraints on the possible lengths or periods of data streams.
One conventional method for solving this problem is to make the length of the data stream a multiple of n by adding extra meaningless data in case the length or period of the data is not a multiple of n. However, there are some cases in which the addition of the extra data may not always be possible. If repeating data is to be generated, other methods can be employed such as storing between the start and last addresses the data having the length of the common multiple between n and the period of the data stream, p. This method has the drawback of wasting the memory because a plurality of periods is required to be written in the memory. Neither method is easy to implement, and the limitation of multiples of n remains a serious problem.